SN8P1602A datasheet(39/76 Pages) SONIX

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SN8P1602B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 39

Version 1.1

OSCM REGISTER DESCRIPTION

The OSCM register is an oscillator control register. It controls oscillator status, system mode, watchdog timer clock

rate.

0CAH

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCM

WTCKS

WDRST

CPUM1

CPUM0

CLKMD

STPHX

Read/Write

R/W

After reset

STPHX: External high-speed oscillator control bit. 0 = free run, 1 = stop. This bit only controls external high-speed

oscillator. If STPHX=1, the internal low-speed RC oscillator is still running.

CLKMD: System high/Low clock mode: bit 0 = normal (dual) mode, 1 = slow mode.

CPUM1, CPUM0: CPU operating mode control bit:

00 = normal

01 = sleep (power down) mode

10 = green mode

11 = reserved.

WDRST: Watchdog timer reset bit

0 = Non-reset

1 = clear the watchdog timer’s counter.

Please refer to the “watchdog timer chapter” for detailed information.

WTCKS: Watchdog clock source

0 = Fcpu

1 = internal RC low clock

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