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SL4034B Fiches technique(PDF) 4 Page - System Logic Semiconductor

No de pièce SL4034B
Description  8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register
PDF  9 Pages
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Fabricant  SLS [System Logic Semiconductor]
Site Internet  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL4034B Fiches technique(HTML) 4 Page - System Logic Semiconductor

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SL4034B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF, RL=200k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
fmax
Maximum Clock Frequency (Figure 2)
5.0
10
15
2
5
7
2
5
7
1
2.5
3.5
MHz
tPHL, tPLH
Maximum Propagation Delay, A(B) Parallel Data
In to B(A) Parallel Data Out; Serial to Parallel
Data Out (Figures 1,2)
5.0
10
15
700
240
170
700
240
170
1400
480
340
ns
tPLZ, tPHZ,
tPZL, tPZH
Maximum Propagation Delay, A/B or AE to “A”
Output (Figure 3)
5.0
10
15
400
160
120
400
160
120
800
320
240
ns
tTHL, tTLH
Maximum Output Transition Time, Any Output
(Figures 1,2)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS(C
L=50pF, RL=200 k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
tsu
Minimum Setup Time, Serial Data to Clock
(Figure 4)
5.0
10
15
160
60
40
160
60
40
320
120
80
ns
tsu
Minimum Setup Time, Parallel Data to Clock
(Figure 4)
5.0
10
15
50
30
20
50
30
20
100
60
40
ns
th
Minimum Hold Time, Clock to Data (Figure 4)
5.0
10
15
50
15
10
50
15
10
100
30
20
ns
tw
Minimum Pulse Width, AE, P/S, A/S
(Figure 5)
5.0
10
15
350
140
80
350
140
80
700
280
160
ns
tw
Minimum Pulse Width, Clock (Figure 2)
5.0
10
15
250
100
70
250
100
70
500
200
140
ns
tr ,tf
Minimum Input Rise or Fall Time, Clock (Figure
2)
5.0
10
15
15
15
15
15
15
15
30
30
30
ns



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