SP9601JS datasheet(3/9 Pages) SIPEX

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SP9601DS/02

SP9601 12-Bit, Low-Power Voltage Output

SPECIFICATIONS (continued)

(Typical at 25˚C; T

MIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

POWER REQUIREMENTS

Note 5

+5V,

±3%; Note 4, 5

-J, -K

0.2

0.3

-A, -B

0.2

0.45

-5V,

±3%; Note 4, 5

-J, -K

0.2

0.3

-A, -B

0.2

0.45

Power Dissipation

SWITCHING

CHARACTERISTICS

CS Setup Time

CSS)25

SCLK Fall to CS

Fall Hold Time

CSH0)20

SCLK Fall to CS Rise

Hold Time

CSH1)0

SCLK High Width

CH)40

SCLK Low Width

CL)40

DIN Setup Time

DS)50

DIN Hold Time

DH)0

CS High Pulse Width

CSW)30

ENVIRONMENTAL AND

MECHANICAL

Operating Temperature

-J, -K

+70

°C

-A, -B

-40

+85

°C

Storage

-60

+150

°C

Package

–_N

8-pin Plastic DIP

–_S

8-pin 0.15" SOIC

Notes:

Integral Linearity, for the SP9601, is measured as the arithmetic mean value of the magnitudes of

the greatest positive deviation and the greatest negative deviation from the theoretical value for any

given input condition.

Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

1 LSB = 2*V

REF/4,096.

REF = 0V.

The following power up sequence is recommended: VSS (-5V), Vdd (+5V), VREF.

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