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SP8530 Fiches technique(PDF) 2 Page - Sipex Corporation

No de pièce SP8530
Description  S2ADC - Simultaneous Sampling Analog to Digital Converter
PDF  12 Pages
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Fabricant  SIPEX [Sipex Corporation]
Site Internet  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP8530 Fiches technique(HTML) 2 Page - Sipex Corporation

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SP8530DS/01
SP8530 S2ADC
TM - Simultaneous Sampling Analog to Digital Converter
© Copyright 2000 Sipex Corporation
2
ABSOLUTE MAXIMUM RATINGS
(TA=+25˚C unless otherwise noted) ..............................................
VDD to DGND ............................................................. -0.3V to +7V
VDA to AGND .............................................................. -0.3V to +7V
Vin to AGND .................................................... -0.3V to VDA +0.3V
Digital Input to VSS ........................................... -0.3V to VDD+0.3V
Digital Output to VSS ........................................ -0.3V to VDD+0.3V
Operating Temp. Range
Commercial (J,K Version) ............................... 0˚C to 70˚C
Industrial (A,B Version) .............................. -40˚C to +85˚C
Storage Temperature ............................................... -65˚C to 150˚C
Lead Temperature(Solder 10sec) ........................................ +300˚C
Power Dissipation to +70˚C ................................................ 500mW
Derate Above 70˚C ......................................................... 10mW/ ˚C
SPECIFICATIONS
Unless otherwise noted the following specifications apply for V
DD = 5V with limits applicable for TA = 25
oC.
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DC Accuracy
Resolution
12
Bits
Integral Linearity
J, A
+0.6
+1.0
LSB
K ,B
+0.4
+0.75
LSB
Differential Linearity Error
J, A
+0.5
+1.0
LSB
No Missing Codes
K ,B
+0.5
+1.0
LSB
No Missing Codes
Gain Error
J, A
+0.2
+1.0
%FSR
Externally Trimmable to Zero
K,B
+0.1
+0.5
%FSR
Externally Trimmable to Zero
Offset Error
J, A
+4
+7
LSB
Externally Trimmable to Zero
K,B
+3
+5
LSB
Externally Trimmable to Zero
Gain Match
J, A
+2
LSB
K,B
+2
LSB
Offset Match
J, A
+1.0
LSB
Externally Trimmable to Zero
K,B
+0.5
LSB
Externally Trimmable to Zero
Analog Input
0 to 2.5
Volts
Conversion Speed
Sample Time
400
ns
Conversion Time
7.75
µs
Complete Cycle
8.25
Simultaneous Convert
Rate:
121
KHz
Simultaneous Pair
Clock Speed
4
MHz
Data Rate:
242
KHz
Total Data Conversion Rate



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