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F71869AD Fiches technique(PDF) 39 Page - Feature Integration Technology Inc.

No de pièce F71869AD
Description  Super I/O Hardware Monitor
PDF  156 Pages
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Fabricant  FINTEK [Feature Integration Technology Inc.]
Site Internet  http://www.fintek.com.tw/eng
Logo FINTEK - Feature Integration Technology Inc.

F71869AD Fiches technique(HTML) 39 Page - Feature Integration Technology Inc.

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Oct., 2011
V0.19P
39
F71869A
Figure 15 Timing on/off sequence
5.5 S3_Gate#, S3P5_Gate# and S0P5_Gate# Timing
The F71869A provides three additional timing switching pins which are named as S3_Gate#,
S3P5_Gate# and S0P5_Gate#. They can be applied in the certain applications about power switch
which depends on the ACPI states. The detail timing can be referred in the following diagrams.
The default timing of S0P5_Gate# in the S5 state is low, but it can be programmed high by the
register 0x0AF6.
S5
S3
S0
S5
S5#
S3#
PSON#
ATXPWGD
TIMING_1
TIMING_2
TIMING_3
TIMING_4
CPU_PWGD
VDDOK_D400
S0
S3



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