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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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UCD3138 Fiches technique(PDF) 56 Page - Texas Instruments |
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UCD3138 Fiches technique(HTML) 56 Page - Texas Instruments |
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56 / 68 page  UCD3138 SLUSAP2 A – MARCH 2012 – REVISED MARCH 2012 www.ti.com 4.24 Power Disable Control or (Clock Gating Control) Power disable control register provides control bits that can enable or disable arrival of clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more. All these controls are enabled as default. If a specific peripheral is not used in a specific application the clock gate can be disabled in order to block the propagation of clock signal to that peripheral and therefore reduce the overall current consumption of the device. 56 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 |
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