ADP1047ARQZ-R7 datasheet(71/84 Pages) AD

71 / 84 page

Data Sheet

ADP1047/ADP1048

Rev. 0 | Page 71 of 84

INRUSH SET REGISTER

Table 107. Register 0xFE2E—Inrush Set

Bits

Bit Name

R/W

Description

[7:5]

RSVD

Reserved.

[4:3]

Timer

R/W

These bits set the timer for the VIN_LOW flag measurement.

Bit 4

Bit 3

Timer

Quarter line cycle

Half line cycle

2 ms

4 ms

[2:0]

Inrush delay time

R/W

These bits set the inrush signal delay time after the BROWN_OUT flag goes low.

Bit 2

Bit 1

Bit 0

Number of Full AC Line Cycles

FAST_OVP_FAULT_RISE REGISTER

Table 108. Register 0xFE2F—FAST_OVP_FAULT_RISE

Bits

Bit Name

R/W

Description

RSVD

Reserved.

[6:0]

Fast OVP rise threshold

R/W

These bits set the rising threshold for the analog comparator at the OVP pin input as follows:

OVP threshold = (Code × 0.492/128) + 1.

This threshold is programmable from 1 V to 1.5 V. Each LSB increments the threshold by 3.844 mV.

A value of 0x00 corresponds to a 1 V threshold; a value of 0x3F corresponds to a 1.492 V threshold.

FAST_OVP_FAULT_FALL REGISTER

Table 109. Register 0xFE30—FAST_OVP_FAULT_FALL

Bits

Bit Name

R/W

Description

RSVD

Reserved.

[6:0]

Fast OVP fall threshold

R/W

These bits set the falling threshold for the analog comparator at the OVP pin input as follows:

OVP threshold = (Code × 0.492/128) + 1.

This threshold is programmable from 1 V to 1.5 V. Each LSB increments the threshold by 3.844 mV.

A value of 0x00 corresponds to a 1 V threshold; a value of 0x3F corresponds to a 1.492 V threshold.

FAST OVP DEBOUNCE TIME SETTING REGISTER

Table 110. Register 0xFE31—Fast OVP Debounce Time Setting

Bits

Bit Name

R/W

Description

[7:2]

RSVD

Reserved.

[1:0]

OVP debounce time

R/W

These bits set the fast OVP debounce time.

Bit 1

Bit 0

Time

120 ns

240 ns

480 ns

640 ns

ADP1047ARQZ-R7 Fiches technique(PDF) 71 Page - Analog Devices

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