ADP1046ACPZ-R7 datasheet(75/96 Pages) AD

75 / 96 page

Data Sheet

ADP1046

Rev. 0 | Page 75 of 96

Bits

Bit Name

R/W

Description

[2:0]

Slew rate

R/W

These bits specify the slew rate at the VS3± pins for the change in the voltage reference setting.

Bit 2

Bit 1

Bit 0

Slew Rate

200 mV/ms

100 mV/ms

50 mV/ms

25 mV/ms

12.5 mV/ms

6.25 mV/ms

3.125 mV/ms

1.5625 mV/ms (4 LSB/ms)

Table 96. Register 0x60—Normal Mode Digital Filter LF Gain Setting

Bits

Bit Name

R/W

Description

[7:0]

LF gain setting

R/W

This register determines the low frequency gain of the loop response. Programmable over a 20 dB

range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

Table 97. Register 0x61—Normal Mode Digital Filter Zero Setting

Bits

Bit Name

R/W

Description

[7:0]

Zero setting

R/W

This register determines the position of the final zero. See Figure 57.

Table 98. Register 0x62—Normal Mode Digital Filter Pole Setting

Bits

Bit Name

R/W

Description

[7:0]

Pole location

R/W

This register determines the position of the final pole. See Figure 57.

Table 99. Register 0x63—Normal Mode Digital Filter HF Gain Setting

Bits

Bit Name

R/W

Description

[7:0]

HF gain setting

R/W

This register determines the high frequency gain of the loop response. Programmable over a 20 dB

range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

Table 100. Register 0x64—Light Load Mode Digital Filter LF Gain Setting

Bits

Bit Name

R/W

Description

[7:0]

LF gain setting

R/W

This register determines the low frequency gain of the loop response. Programmable over a 20 dB

range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

Table 101. Register 0x65—Light Load Mode Digital Filter Zero Setting

Bits

Bit Name

R/W

Description

[7:0]

Zero setting

R/W

This register determines the position of the final zero. See Figure 57.

Table 102. Register 0x66—Light Load Mode Digital Filter Pole Setting

Bits

Bit Name

R/W

Description

[7:0]

Pole location

R/W

This register determines the position of the final pole. See Figure 57.

Table 103. Register 0x67—Light Load Mode Digital Filter HF Gain Setting

Bits

Bit Name

R/W

Description

[7:0]

HF gain setting

R/W

This register determines the high frequency gain of the loop response. Programmable over a 20 dB

range. Each LSB corresponds to a 0.3 dB increase. See Figure 57.

ADP1046ACPZ-R7 Fiches technique(PDF) 75 Page - Analog Devices

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