TSV6290 datasheet(7/23 Pages) STMICROELECTRONICS

7 / 23 page

TSV6290, TSV6290A, TSV6291, TSV6291A

Electrical characteristics

Doc ID 17117 Rev 1

7/23

Table 6.

VCC+ = +5 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25° C, RL connected to VCC/2

(unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

DC performance

Vio

Offset voltage

TSV6290-TSV6291

TSV6290A-TSV6291A

0.8

Tmin < Top < Tmax

TSV6290-TSV6291

TSV6290A-TSV6291A

DVio

Input offset voltage drift

μV/°C

Iio

Input offset current(1)

110

Tmin < Top < Tmax

100

Iib

Input bias current(1)

110

Tmin < Top < Tmax

100

CMR

Common mode rejection ratio

20 log (

ΔVic/ΔVio)

0V to 5V, Vout = 2.5 V

Tmin < Top < Tmax

SVR

Supply voltage rejection ratio 20

log (

ΔVCC/ΔVio)

VCC = 1.8 to 5 V

102

Tmin < Top < Tmax

Avd

Large signal voltage gain

RL=10 kΩ, Vout = 0.5 V to 4.5 V

Tmin < Top < Tmax

VOH

High level output voltage

RL =10kΩ

Tmin < Top < Tmax

VOL

Low level output voltage

RL =10kΩ

635

Tmin < Top < Tmax

Iout

Isink

Vout =5V

Tmin < Top < Tmax

Isource

Vout = 0 V

Tmin < Top < Tmax

ICC

Supply current (per operator)

No load, Vout =2.5 V

µA

Tmin < Top < Tmax

µA

AC performance

GBP

Gain bandwidth product

RL =10kΩ, CL = 100 pF

1.3

MHz

Gain

Minimum gain for stability

Phase margin = 60°, Rf = 10 kΩ,

RL =10kΩ, CL =20 pF

-3

V/V

Slew rate

RL =10kΩ, CL = 100 pF,

Vout = 0.5 V to 4.5 V

0.5

μs

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