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PCF8593 Fiches technique(PDF) 3 Page - NXP Semiconductors |
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PCF8593 Fiches technique(HTML) 3 Page - NXP Semiconductors |
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3 / 35 page ![]() PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 3 of 35 NXP Semiconductors PCF8593 Low power clock and calendar 6. Pinning information 6.1 Pinning 6.2 Pin description Top view. For mechanical details, see Figure 24. Fig 2. Pin configuration for DIP8 (PCF8593P) Top view. For mechanical details, see Figure 25. Fig 3. Pin configuration for SO8 (PCF8593T) PCF8593P OSCI VDD OSCO INT RESET SCL VSS SDA 013aaa380 1 2 3 4 6 5 8 7 PCF8593T 013aaa381 1 2 3 4 6 5 8 7 OSCI OSCO RESET VSS VDD INT SCL SDA Table 3. Pin description Symbol Pin Type Description DIP8 (PCF8593P) SO8 (PCF8593T) OSCI 1 1 input oscillator input, 50 Hz or event-pulse input OSCO 2 2 output oscillator output RESET 3 3 input reset VSS 4 4 supply ground supply voltage SDA 5 5 input/output serial data line SCL 6 6 input serial clock line INT 7 7 output open-drain interrupt output (active LOW) VDD 8 8 supply supply voltage |
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