FULLFLEX datasheet(50/52 Pages) CYPRESS

50 / 52 page

FullFlex

Document Number: 38-06082 Rev. *K

Page 50 of 52

402238

SEE ECN

KGH

Updated AC Test Load and Waveforms

Included FullFlex36 SDR 484-Ball BGA Pinout (Top View)

Included FullFlex18 SDR 484-Ball BGA Pinout (Top View)

Included Timing Parameter tCORDY

458131

SEE ECN

YDT

Changed ordering information with Pb-free part numbers

Removed VC_SEL

Added IO and core voltage adders

Removed references to bin drop for LVTTL/2.5 V LVCMOS and 1.5 V core modes

Updated Cin and Cout

Updated ICC, ISB1, ISB2 and ISB3 tables

Updated busy address read back timing diagram

Added HTSL input waveform

Removed HSTL (AC) from DC tables

Added 484-ball 27 mmx27 mmx2.33 mm PBGA package

470031

SEE ECN

YDT

Changed VOL of 1.8 V LVCMOS to 0.45 V

Updated tRSF

VREF is DNU when HSTL is not used

Formatted pin description table

Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts

Changed 36Mx72 JTAG IDCODE

500001

SEE ECN

YDT

DLL Change, added Clock Input Cycle to Cycle Jitter

Modified DLL description

Changed Input Capacitance Table

Changed tCCS number

Added note 31

627539

SEE ECN

QSL

change all NC to DNU

corrected switching waveform for (CQEN = High) from both Pipeline and Flow

through mode to only pipeline mode

Modified master reset description

Modified switching characteristics tables, extracted signals effected by the DLL

into one table and combine all other signals into one table

updated package name

Added footnote for tHD, tHAC and tSAC

changed note 26 description

Document History Page (continued)

Document Title: FullFlex™ Synchronous SDR Dual Port SRAM

Document Number: 38-06082

REV.

ECN NO. Submission

Date

Orig. of

Change

Description of Change

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