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PCIMX536AVV8C Fiches technique(PDF) 46 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8C Fiches technique(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 178 page ![]() i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2 46 Freescale Semiconductor Electrical Characteristics Table 32 shows the electrical parameters of CAMP. 4.6.4 DPLL Electrical Parameters Table 33 shows the electrical parameters of digital phase-locked loop (DPLL). Table 32. CAMP Electrical Parameters (CKIH1, CKIH2) Parameter Min Typ Max Unit Input frequency 8.0 — 40.0 MHz VIL (for square wave input) 0 — 0.3 V VIH (for square wave input)1 1 NVCC_CKIH is the supply voltage of CAMP. NVCC_CKIH – 0.25 — NVCC_CKIH V Sinusoidal input amplitude 0.4 — VDD Vp-p Output duty cycle 45 50 55 % Table 33. DPLL Electrical Parameters Parameter Test Conditions/Remarks Min Typ Max Unit Reference clock frequency range1 1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 32. —10 — 100 MHz Reference clock frequency range after pre-divider —10 — 40 MHz Output clock frequency range (dpdck_2) — 300 — 1025 MHz Pre-division factor2 2 The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user. Therefore, the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD. —1 — 16 — Multiplication factor integer part — 5 — 15 — Multiplication factor numerator3 3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be zero. Should be less than denominator –67108862 — 67108862 — Multiplication factor denominator2 — 1 — 67108863 — Output Duty Cycle — 48.5 50 51.5 % Frequency lock time4 (FOL mode or non-integer MF) —— — 398 Tdpdref Phase lock time — — — 100 µs Frequency jitter5 (peak value) — — 0.02 0.04 Tdck Phase jitter (peak value) FPL mode, integer and fractional MF — 2.0 3.5 ns Power dissipation fdck = 300 MHz at avdd = 1.8 V, dvdd = 1.2 V fdck = 650 MHz at avdd = 1.8 V, dvdd = 1.2 V — — 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) mW |
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