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BTS6480SF Fiches technique(PDF) 12 Page - Infineon Technologies AG |
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BTS6480SF Fiches technique(HTML) 12 Page - Infineon Technologies AG |
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12 / 73 page ![]() Data Sheet 12 Rev. 1.0, 2010-04-12 SPOC - BTS6480SF Electrical Characteristics 4.2 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 4.2.1 Junction to Soldering Point 1) 1) Not subject to production test, specified by design. R thJSP – – 20 K/W measured to pin 1, 2, 9, 28, 35, 36 4.2.2 Junction to Ambient 1) R thJA –35 – K/W 2) 2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. |
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