STHDLS101QTR datasheet(7/25 Pages) STMICROELECTRONICS

7 / 25 page

STHDLS101

Pin configuration

7/25

3.1

Pin description

Table 2.

Pin description

number

Name

Type

Function

1GND

Power

Ground

VCC33

Power

3.3 V±10% DC supply

FUNCTION1

Vendor-specific

control or test

pins

Function pins are to enable vendor-specific features or

test modes.

For normal operation, these pins are tied to GND or

VCC33.

For consistent interoperability, GND is the preferred

default connection for these signals.

FUNCTION2

Vendor-specific

control or test

pins

Function pins are to enable vendor-specific features or

test modes.

For normal operation, these pins are tied to GND or

VCC33.

For consistent interoperability, GND is the preferred

default connection for these signals.

5GND

Power

Ground

REXT

Analog

Connection to external resistor. Resistor value

specified by device manufacturer.

Acceptable connections to this pin are:

- Resistor to GND

- Resistor to 3.3 V

- NC (direct connections to VCC or GND are through a

0 Ω resistor for layout compatibility

HPD_SOURCE

Output

0 to 3.3 V (nominal) output signal. This is level-shifted

version of the HPD_SINK signal.

SDA_SOURCE

I/O

3.3 V DDC data I/O. Pulled-up by external termination

to 3.3 V. Connected to SDA_SINK through voltage-

limiting integrated NMOS pass-gate.

SCL_SOURCE

Input

3.3 V DDC clock I/O. Pulled-up by external termination

to 3.3 V. Connected to SCL_SINK through voltage-

limiting integrated NMOS pass-gate.

ANALOG2

Analog

Analog connection determined by vendor. Acceptable

connections to this pin are:

- Resistor or capacitor to GND

- Resistor or capacitor to 3.3 V

- Short to 3.3 V or to GND

- NC

VCC33

Power

3.3 V ±10% DC supply

GND

Power

Ground

OUT_D4+

Output

HDMI 1.3 compliant TMDS output.

OUT_D4+ makes a differential output signal with

OUT_D4-.

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