STW4811MBRATSLASHHF datasheet(34/85 Pages) STMICROELECTRONICS

34 / 85 page

Functional description

STw4811M/STw4811N

34/85

CD00131784

Power control register at address 08h

Power control register at address 09h

Table 25.

Power control register at address 08h

Address 1Fh

Address 1Eh

9876

Not used

0100

en_clk

squarer

en_

nitoring

en_

vana

not

used

Bits

Name

Value

Settings

Default

en_clock_squarer

Disabled ([0; vio_vmem] digital signal)

Enabled

(master clock input not in the range [0; vio_vmem])

en_monitoring

Disabled / MONITORING = OFF

Enabled / VCORE & VIO_VMEM monitoring = ON

en_vana

Disabled / VANA = OFF

Enabled / VANA = ON

Table 26.

Power control register at address 09h

Address 1Fh

Address 1Eh

9876

4321

Not used

0100

vaux_

sleep

not

used

vio_

vmem_

sleep

(1)

Must be left at default value if the master clock is used.

vcore_

sleep

(1)

Bits

Name

Value

Settings

Default

4vaux_sleep

When PWREN is low:

VAUX stays in high power mode

VAUX goes in sleep mode

vio_vmem_sleep

When PWREN is low:

VIO_VMEM stays in high power mode

VIO_VMEM goes in sleep mode

1vcore_sleep

When PWREN is low:

VCORE stays in high power mode

VCORE goes in sleep mode

STW4811MBRAT/HF Fiches technique(PDF) 34 Page - STMicroelectronics

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