M24M01-R datasheet(6/37 Pages) STMICROELECTRONICS

6 / 37 page

Description

M24M01-R, M24M01-W, M24M01-HR

6/37

Doc ID 12943 Rev 7

Description

The M24M01-HR, M24M01-R and M24M01-W are I2C-compatible electrically erasable

programmable memory (EEPROM) devices organized as 128 Kb × 8 bits.

The I2C bus is a two-wire serial interface, comprising a bidirectional data line and a clock

line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with

the I2C bus definition.

The M24M01-HR, M24M01-R and M24M01-W behave as slaves in the I2C protocol, with all

memory operations synchronized by the serial clock. Read and Write operations are

generated by the bus master and initiated by a Start condition, followed by the device select

code, address bytes and data bytes. Data transfers are terminated by a Stop condition after

an Ack for Write, and after a NoAck for Read.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way.

The M24M01-HR, M24M01-R and M24M01-W are delivered in SO8 packages and the

M24M01-R is also available in wafer form (see Table 21: Available M24M01-x products

(package, voltage range, frequency, temperature grade) for details).

Caution:

As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet

(UV) light, EEPROM dice delivered in wafer form by STMicroelectronics must never be

exposed to UV light.

Figure 1.

Logic diagram

AI13415d

SDA

VCC

M24M01-R

M24M01-HR

M24M01-W

SCL

VSS

E1-E2

M24M01-R Fiches technique(PDF) 6 Page - STMicroelectronics