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M95512-WCS3G/AB Fiches technique(PDF) 11 Page - STMicroelectronics |
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M95512-WCS3G/AB Fiches technique(HTML) 11 Page - STMicroelectronics |
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11 / 48 page ![]() M95512-W, M95512-R Connecting to the SPI bus Doc ID 11124 Rev 13 11/48 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 5. SPI modes supported AI01438B C MSB CPHA D 0 1 CPOL 0 1 Q C MSB |
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