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AD9552PCBZ Fiches technique(PDF) 8 Page - Analog Devices |
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AD9552PCBZ Fiches technique(HTML) 8 Page - Analog Devices |
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8 / 32 page ![]() AD9552 Rev. C | Page 8 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 Y4 2 Y5 3 A0 4 A1 5 A2 6 RESET 7 VDD 8 LDO NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. 24 GND 23 OUT2 22 21 VDD 20 LOCKED 19 LDO 18 VDD 17 LDO TOP VIEW (Not to Scale) AD9552 OUT2 Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Type1 Description 29, 30, 31, 32, 1, 2 Y0, Y1, Y2, Y3, Y4, Y5 I Control Pins. These pins select preset values for the PLL feedback divider and the OUT1 dividers based on the input reference frequency selected via the A[0:2] pins and have internal 100 kΩ pull-up resistors. 3, 4, 5 A0, A1, A2 I Control Pins. These pins select the input reference frequency and have internal 100 kΩ pull- up resistors. 6 RESET I Digital Input, Active High. Resets internal logic to default states. This pin has an internal 100 kΩ pull-up resistor, so the default state of the device is reset. 7, 18, 21, 28 VDD P Power Supply Connection: 3.3 V Analog Supply. 8, 17, 19 LDO P/O LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to ground. 9, 10 XTAL I Crystal Resonator Input. Connect a crystal resonator across these pins. 11 REF I Reference Clock Input. Connect this pin to an active clock input signal, or connect it to VDD when using a crystal resonator across the XTAL pins. 12 CS I Digital Input, Active Low, Chip Select. 13 SCLK I Serial Data Clock. 14 SDIO I/O Digital Serial Data Input/Output. 15 OUTSEL I Logic 0 selects LVDS and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2 when the outputs are not under SPI port control. Can be overridden via the programming registers. This pin has an internal 100 kΩ pull-up resistor. 16 FILTER I/O Loop Filter Node for the PLL. Connect an external 12 nF capacitor from this pin to Pin 17 (LDO). 20 LOCKED O Active High Locked Status Indicator for the PLL. 26, 22 OUT1, OUT2 O Complementary Square Wave Clocking Outputs. 27, 23 OUT1, OUT2 O Square Wave Clocking Outputs. 24, 25 GND P Analog Ground. EP Exposed Die Pad The exposed die pad must be connected to GND. 1 I = input, I/O = input/output, O = output, P = power, P/O = power/output. |
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