641 datasheet(29/106 Pages) INTEL

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Datasheet

Electrical Specifications

2.7

Clock Specifications

2.7.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the Pentium 4 processor core

frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier

will be set at its default ratio during manufacturing. Refer to Table 17 for the processor

supported ratios.

The processor uses a differential clocking implementation. For more information on

processor clocking, contact your Intel representative.

Table 17.

Core Frequency to FSB Multiplier Configuration

Multiplication of System Core

Frequency to FSB Frequency

Core Frequency

(200 MHz BCLK/

800 MHz FSB)

Notes1,2

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

1/12

2.40 GHz

1/13

2.60 GHz

1/14

2.80 GHz

1/15

3 GHz

1/16

3.20 GHz

1/17

3.40 GHz

1/18

3.60 GHz

1/19

3.80 GHz

1/20

4 GHz

1/21

4.20 GHz

1/22

4.40 GHz

1/23

4.60 GHz

1/24

4.80 GHz

1/25

5 GHz

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