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PIC16F720-I/ML Fiches technique(PDF) 37 Page - Microchip Technology |
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PIC16F720-I/ML Fiches technique(HTML) 37 Page - Microchip Technology |
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37 / 244 page  2010 Microchip Technology Inc. DS41430A-page 37 PIC16F/LF720/721 4.0 INTERRUPTS The PIC16F/LF720/721 device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16F/LF720/721 device family has 12 interrupt sources, differentiated by corresponding interrupt enable and flag bits: • Timer0 Overflow Interrupt • External Edge Detect on INT Pin Interrupt • PORTA and PORTB Change Interrupt • Timer1 Gate Interrupt • A/D Conversion Complete Interrupt • AUSART Receive Interrupt • AUSART Transmit Interrupt • SSP Event Interrupt • CCP1 Event Interrupt • Timer2 Match with PR2 Interrupt • Timer1 Overflow Interrupt A block diagram of the interrupt logic is shown in Figure 4-1. FIGURE 4-1: INTERRUPT LOGIC TMR0IF TMR0IE INTF INTE RABIF RABIE GIE PEIE Wake-up (if in Sleep mode)(1) Interrupt to CPU TMR1GIE TMR1GIF ADIF ADIE CCP1IF CCP1IE IOC-RB4 IOCB4 IOC-RB5 IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 RCIF RCIE TMR2IE TMR2IF SSPIE SSPIF TXIE TXIF TMR1IE TMR1IF Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, these peripherals will not wake the part from Sleep. See Section 19.1 “Wake-up from Sleep”. IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA0 IOCA0 |
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