MC68HC705P9CS datasheet(71/160 Pages) FREESCALE

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Resets and Interrupts

Interrupts

MC68HC705P9 — Rev. 4.0

Technical Data

MOTOROLA

Resets and Interrupts

5.4.3 Timer Interrupts

The capture/compare timer can generate the following interrupts:

•

Input capture interrupt

•

Output compare interrupt

•

Timer overflow interrupt

Setting the I bit in the condition code register disables timer interrupts.

5.4.3.1 Input Capture Interrupt

An input capture interrupt request occurs if the input capture flag, ICF,

becomes set while the input capture interrupt enable bit, ICIE, is also set.

ICF is in the timer status register, and ICIE is in the timer control register.

5.4.3.2 Output Compare Interrupt

An output compare interrupt request occurs if the output compare flag,

OCF, becomes set while the output compare interrupt enable bit, OCIE,

is also set. OCF is in the timer status register, and OCIE is in the timer

control register.

5.4.3.3 Timer Overflow Interrupt

A timer overflow interrupt request occurs if the timer overflow flag, TOF,

becomes set while the timer overflow interrupt enable bit, TOIE, is also

set. TOF is in the timer status register, and TOIE is in the timer control

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