PC312XDP512F0CFVR datasheet(951/1348 Pages) FREESCALE

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23.0.5.55 Port J Input Register (PTIJ)

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can be used to detect

overload or short circuit conditions on output pins.

23.0.5.56 Port J Data Direction Register (DDRJ)

Read: Anytime.

Write: Anytime.

This register configures each port J pin as either input or output.

The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6

(RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will

not change.

The SCI2 forces the I/O state to be an output for each port line associated with an enabled output

(TXD2). It also forces the I/O state to be an input for each port line associated with an enabled input

(RXD2). In these cases the data direction bits will not change.

The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral

module is disabled.

76543210

PTIJ7

PTIJ6

PTIJ5

PTIJ4

PTIJ2

PTIJ1

PTIJ0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

00000000

= Unimplemented or Reserved

Figure 23-57. Port J Input Register (PTIJ)

76543210

DDRJ7

DDRJ6

DDRJ5

DDRJ4

DDRJ2

DDRJ1

DDRJ0

Reset

00000000

= Unimplemented or Reserved

Figure 23-58. Port J Data Direction Register (DDRJ)

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