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PC312XDP512F0CFVR Fiches technique(PDF) 278 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Fiches technique(HTML) 278 Page - Freescale Semiconductor, Inc |
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278 / 1348 page ![]() Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 278 Freescale Semiconductor Operation RS.L ⇒ M[RB, #OFFS5] RS.L ⇒ M[RB, RI] RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]1 Stores the low byte of register RD to memory. CCR Effects Code and CPU Cycles STB Store Byte to Memory (Low Byte) STB 1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source register is written to the memory: RS.L ⇒ M[RB, RS-1]; RS-1 ⇒ RS NZ V C ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles STB RS, (RB, #OFFS5), IDO5 0 1 0 1 0 RS RB OFFS5 Pw STB RS, (RB, RI) IDR 0 1 1 1 0 RS RB RI 0 0 Pw STB RS, (RB, RI+) IDR+ 0 1 1 1 0 RS RB RI 0 1 Pw STB RS, (RB, -RI) -IDR 0 1 1 1 0 RS RB RI 1 0 Pw |
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