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56F807 Fiches technique(PDF) 39 Page - Freescale Semiconductor, Inc |
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56F807 Fiches technique(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 60 page ![]() Serial Peripheral Interface (SPI) Timing 56F807 Technical Data Technical Data, Rev. 16 Freescale Semiconductor 39 Figure 3-19 SPI Master Timing (CPHA = 0) Figure 3-20 SPI Master Timing (CPHA = 1) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in tF tC tCL tCL tR tR tF tDS tDH tCH tDI tDV tDI(ref) tR Master MSB out Bits 14–1 Master LSB out SS (Input) tCH SS is held High on master tF SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in tR tC tCL tCL tF tCH tDV(ref) tDV tDI(ref) tR tF Master MSB out Bits 14– 1 Master LSB out SS (Input) tCH SS is held High on master tDS tDH tDI tR tF |
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