ADM1031ARQZ-R7 datasheet(22/30 Pages) ONSEMI

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ADM1031

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Figure 37. Fan Speed Measurement

CLOCK

CONFIG 2

REG. BIT 2

FAN

INPUT

START OF

MONITORING

CYCLE

FAN

MEASUREMENT

PERIOD

In situations where different output drive circuits are used

for fan drive, it can be desirable to invert the PWM drive

signal. Setting Bit 3 of Configuration Register 1 (0

×00) to 1,

inverts the PWM_OUT signal. This makes the PWM_OUT

pin high for 100% duty cycle. Bit 3 of Configuration

n−MOS device to drive the fan.

If using a p−MOS device, Bit 3 of Configuration Register

1 should be cleared to 0.

FAN_FAULTs

The FAN_FAULT output (Pin 8) is an active−low,

open−drain output used to signal fan failure to the system

processor. Writing a Logic 1 to Bit 4 of Configuration

×00) enables the FAN_FAULT output pin. The

FAN_FAULT output is enabled by default. The

FAN_FAULT output asserts low only when five consecutive

interrupts are generated by the ADM1031 device due to the

fan running underspeed, or if the fan is completely stalled.

Note that the Fan Tach High Limit must be exceeded by at

least one before a FAN_FAULT can be generated. For

example, if we are only interested in getting a FAN_FAULT

if the fan stalls, then the fan speed value is 0

×FF for a failed

fan. Therefore, we should make the Fan Tach High

Limit = 0

×FE to allow FAN_FAULT to be asserted after five

consecutive fan tach failures.

Figure 38 shows the relationship between INT,

FAN_FAULT, and the PWM drive channel. The

PWM_OUT channel is driving a fan at some PWM duty

cycle, 50% for example, and the fan’s tach signal (or fan

current for a 2−wire fan) is being monitored at the

TACH/AIN pin. Tach pulses are being generated by the fan,

during the high time of the PWM duty cycle train. The tach

is pulled high during the off time of the PWM train because

the fan is connected high−side to the n−MOS device.

Suppose the fan has twice previously failed its fan speed

measurement. Looking at Figure 38, PWM_OUT is brought

high for two seconds, to restart the fan if it has stalled.

Sometime later a third tach failure occurs. This is evident by

the tach signal being low during the high time of the PWM

pulse, causing the fan speed reading register to reach its

maximum count of 255. Since the tach limit has been

exceeded, an interrupt is generated on the INT pin. The fan

fault bit (Bit 1) of Interrupt Status Register 1 (Register 0

×02)

is also asserted. Once the processor has acknowledged the

INT by reading the status register, the INT is cleared.

PWM_OUT is then brought high for another two seconds to

restart the fan. Subsequent fan failures cause INT to be

reasserted and the PWM_OUT signal is brought high for

two seconds (fan spin−up default) each time to restart the

fan. Once the fifth tach failure occurs, the failure is deemed

to be catastrophic and the FAN_FAULT pin is asserted low.

PWM_OUT is brought high to attempt to restart the fan. The

INT pin continues to generate interrupts after the assertion

of FAN_FAULT since tach measurement continues even

after fan failure. Should the fan recover from its failure

condition, the FAN_FAULT signal is negated, and the fan

returns to its normal operating speed.

Figure 39 shows a typical application circuit for the

ADM1031. Temperature monitoring can be based around a

CPU diode or discrete transistor measuring thermal

hotspots. Either 2− or 3−wire fans can be monitored by the

ADM1031, as shown.

Figure 38. Operation of FAN_FAULT and Interrupt Pins

PWM_OUT

TACH/AIN

INT

FAN_FAULT

STATUS REG READ TO

CLEAR INTERRUPT

FULL SPEED

2 SECS

3RD TACH

FAILURE

4TH TACH

FAILURE

5TH TACH

FAILURE

CONTINUING

TACH FAILURE

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