SC68C752B datasheet(14/48 Pages) NXP

No de pièce	SC68C752B

Description	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode 關P interface

PDF	48 Pages

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Fabricant	NXP [NXP Semiconductors]

Site Internet	http://www.nxp.com

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SC68C752B_4

Product data sheet

Rev. 04 — 20 January 2010

14 of 48

NXP Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.5.1 Interrupt mode operation

In Interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the

receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to

continuously poll the Line Status Register (LSR) to see if any interrupt needs to be

serviced. Figure 8 shows Interrupt mode operation.

6.5.2 Polled mode operation

In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be

checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO

Interrupt mode of operation where the status of the receiver and transmitter is

automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO

polled mode operation.

Fig 8.

Interrupt mode operation

IIR

IER

THR

RHR

PROCESSOR

R/W

IRQ

002aab096

Fig 9.

FIFO polled mode operation

IIR

IER

THR

RHR

PROCESSOR

R/W

002aab097

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