PCF8563BS datasheet(13/32 Pages) NXP

13 / 32 page

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

13 of 32

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1]

registers marked ‘x’ are undeﬁned at power-up and unchanged by subsequent resets.

Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 9).

8.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P); see Figure 10.

05h

days

xxxxxxxx

06h

weekdays

07h

century_months

08h

years

09h

minute_alarm

0Ah

hour_alarm

0Bh

day_alarm

0Ch

weekday_alarm

0Dh

CLKOUT_control

0Eh

timer_control

0Fh

timer

Table 25.

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Fig 9.

Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

PCF8563BS Fiches technique(PDF) 13 Page - NXP Semiconductors

PCF8563BS Fiches technique(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Fiches technique Télécharger

Lien URL