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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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09HSI-S042-R0-CHT Fiches technique(PDF) 6 Page - Hirose Electric |
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09HSI-S042-R0-CHT Fiches technique(HTML) 6 Page - Hirose Electric |
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6 / 71 page  Signal Integrity Report – IT3 (17mm) Page 6 3.1.1.1 Fully populated pin assignment For fully-populated pin assignment, as shown in Figure 5, Ports 1-2 are grouped into Pair 1, and Ports 3-4 are grouped into Pair 2, …, etc. Figure 6 shows the corresponding SDD for pair 8 (or Ports 15-16), where the insertion loss (IL), return loss (RL), and crosstalk can be clearly seen, and are summarized in Table 1. The impedance and trace delay values for each of the 15 differential pairs are shown in Table 2. Figure 7 shows the return loss (RL) comparison with the IEEE802.3ap spec for the center pair 8. Figure 8 - Figure 11 show the power sum and insertion-to-crosstalk ratio (ICR) profile comparison with the IEEE802.3ap spec of NEXT and FEXT, respectively. Figure 5 Fully populated pin assignment Figure 6 SDD for pair 8 (ports 15-16) of connector only |
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