Production Data

WM9703

WOLFSON MICROELECTRONICS LTD

PD Rev 3.4 January 2001

19

Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the WM9703 is

in the Codec Ready state or not. If the Codec Ready bit is a 0, this indicates that the WM9703 is not

ready for normal operation. This condition is normal following the desertion of power on reset for

example, while the WM9703’s voltage references settle. When the AC-link Codec Ready indicator bit

is a 1, it indicates that the AC-link and the WM9703 control and status registers are in a fully

operational state. The AC’97 controller must further probe the Powerdown Control/Status Register to

determine exactly which subsections, if any, are ready.

Prior to any attempts at putting the WM9703 into operation the AC’97 controller should poll the first

bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that the WM9703 has gone

Codec Ready.

Once the WM9703 is sampled Codec Ready then the next 12 bit positions sampled by the AC’97

controller indicate which of the corresponding 12 time slots are assigned to input data streams, and

that they contain valid data. Figure 15 illustrates the time slot based AC-link protocol.

There are several subsections within the WM9703 that can independently go busy/ready. It is the

responsibility of the WM9703 controller to probe more deeply into the WM9703 register file to

determine which the WM9703 subsections are actually ready.

SYNC

BIT_CLK

SDATA_IN

CODEC

READY

SLOT (1)

SLOT (2)

WM9703 SAMPLES

SYNC ASSERTION HERE

AC’97 CONTROLLER

SAMPLES FIRST SDATA_IN

BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

Figure 16 Start of an Audio Input Frame

A new audio input frame begins with a low to high transition of SYNC as shown in Figure 16. SYNC

is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK,

AC’97 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link

are aware of the start of a new audio frame.

On the next rising of BIT_CLK, AC’97 transitions

SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented

to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC’97 Controller on the

following falling edge of BIT_CLK.

This sequence ensures that data transitions and subsequent

sample points for both incoming and outgoing data streams are time aligned.

SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for

assigned and/or unassigned time slots) stuffed with 0s by the WM9703. SDATA_IN should be

sampled on the falling edges of BIT_CLK.

SLOT 1: STATUS ADDRESS PORT

The status port is used to monitor status for the WM9703 functions including, but not limited to, mixer

settings, and power management.

Audio input frame slot 1 echoes the control register index, for historical reference, for the data to

be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the WM9703 during slot

0).

STATUS ADDRESS PORT BIT ASSIGNMENTS:

Bit (19)

RESERVED (stuffed with 0s)

Bit (18:12)

Control register index (echo of register index for which data is

being returned)

Bit (11:2)

Variable sample rate SLOTREQ bits.

Bit (1:0)

RESERVED (stuffed with 0s)

The first bit (MSB) generated by the WM9703 is always stuffed with an 0. The following 7 bit

positions communicate the associated control register address.

The next 10 bits support the AC’97

Rev 2.1 variable sample rate signalling protocol, and the trailing 2 bit positions are stuffed with 0s by

AC’97.