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WM8731 Fiches technique(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8731 Fiches technique(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 56 page ![]() WM8731 Advanced Information WOLFSON MICROELECTRONICS LTD AI Rev 2.0 February 2001 13 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK ADCDAT ADCLRC DACDAT DACLRC WM8731 CODEC DSP ENCODER/ DECODER Note: ADC and DAC can run at different rates Figure 3 Master Mode Connection BCLK (Output) ADCDAT ADCLRC/ DACLRC (Outputs) t DL DACDAT t DDA t DHT t DST Figure 4 Digital Audio Data Timing – Master Mode Test Conditions AVDD, HPVDD, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from BCLK falling edge tDL 010 ns ADCDAT propagation delay from BCLK falling edge tDDA 010 ns DACDAT setup time to BCLCK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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