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ADRF6655ACPZ-R7 Fiches technique(PDF) 5 Page - Analog Devices

No de pièce ADRF6655ACPZ-R7
Description  Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO
PDF  44 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADRF6655ACPZ-R7 Fiches technique(HTML) 5 Page - Analog Devices

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ADRF6655
Rev. 0 | Page 5 of 44
TIMING CHARACTERISTICS
Table 2. Serial Interface Timing, VCC = 5 V ± 5%
Parameter
Limit
Unit
Test Conditions/Comments
t1
20
ns minimum
LE setup time
t2
10
ns minimum
DATA to CLK setup time
t3
10
ns minimum
DATA to CLK hold time
t4
25
ns minimum
CLK high duration
t5
25
ns minimum
CLK low duration
t6
10
ns minimum
CLK to LE setup time
t7
20
ns minimum
LE pulse width
CLK
DATA
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t2
t3
t7
t6
t1
t4
t5
Figure 2. Timing Diagram



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