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CHR0100ASJF/24 Fiches technique(PDF) 4 Page - United Monolithic Semiconductors |
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CHR0100ASJF/24 Fiches technique(HTML) 4 Page - United Monolithic Semiconductors |
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4 / 6 page ![]() CHR0100a 5.8GHz Image rejection mixer Ref. : DSCHR01000161 -9-Jun-00 4/6 Specifications subject to change without notice Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Typical Bias Configuration The typical bias voltage applied to the chip is Vd = 4V. If the LO power is low (ex: < 5dBm) one can apply a negative voltage (-0.3V) on Vg to improve and secure the conversion characteristic. Each Vg and Vd port should have a 10nF decoupling capacitor to the ground. Connection of only one of the two VgQ and Q pads is necessary CHR0100a Q Q I LO RF 10nF VgI 10nF VgQ 10nF Vd 10nF VgQ Chip Mechanical Data CHR0100a Chip size 1770 ± 20 µm x 1370 ± 20 µm Chip thickness 100 ± 10 µm |
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