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Revision 1.02

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AS1530/AS1531

ADJ

Capacitive Bypass at

REFADJ

0.01

10

µF

REFADJ Output Voltage

1.22

V

REFADJ Input Range

For small adjustments, from 1.22V

±100

mV

REFADJ Buffer Disable

Threshold

To power down the internal reference

1.4

1

V

Buffer Voltage Gain

2.045

V/V

External Reference: Reference buffer disabled, reference applied to pin REF

REF Input Voltage Range

8

1.0

+

50mV

V

REF Input Current

200

350

µA

320

5

Digital Inputs: DIN, SCLK, CSN

Input High Voltage

0.7 x

V

Input Low Voltage

0.3 x

V

Input Hysteresis

0.2

V

Input Leakage

-1

+1

µA

Input Capacitance

5

pF

Digital Outputs: DOUT, SSTRB

Output Voltage Low

0.45

V

Output Voltage High

4

V

Tri-State Leakage Current

-10

+10

µA

Tri-State Output Capacitance

5

pF

Power Supply

Positive Supply Voltage

9

4.5

5.5

V

Supply Current

Normal Operation with

External Reference

10

2.8

3.3

mA

Normal Operation with

Internal Reference

10

3.3

3.8

Reduced-Power Mode

11

0.4

0.8

Full Power-Down Mode

0.5

2

µA

PSR

Power-Supply Rejection

-2

±0.1

+2

mV

2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error

and offset error have been nulled.

3. Offset nulled.

4. Ground on channel; sinewave applied to all off channels.

5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty

cycle.

7. External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA

is a result of production test limitations.

8. AS1530/AS1531 performance is limited by the device noise floor, typically 300µVp-p.

Table 3. AS1530 Electrical Characteristics (Continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Units