14

5167E–SFLSH–5/09

AT25FS010

cycle, all instructions will be ignored except RDSR. The AT25FS010 will automatically return to

the write disable state at the completion of the CHIP ERASE cycle.

5. Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 5-1.

Synchronous Data Timing

Figure 5-2.

WREN Timing

Figure 5-3.

WRDI Timing

V

OH

V

OL

HI-Z

HI-Z

t V

VALID IN

V

IH

V

IL

tH

t

SU

t DIS

V

IH

V

IL

t WH

t CSH

V

IH

V

IL

t CSS

t CS

t WL

t HO

CS

SCK

SI

SO

0

1

2

3

4

5

6

7

HI-Z

WREN OP-CODE

CS

SCK

SI

SO

HI-Z

WRDI OP-CODE

CS

SCK

SI

SO