AT89LP4052 datasheet(43/94 Pages) ATMEL

43 / 94 page

3547J–MICRO–10/09

AT89LP2052/LP4052

The interconnection between master and slave CPUs with SPI is shown in Figure 19-1. The four

pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock

(SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock

input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also

notice that MOSI connects to MOSI and MISO to MISO. In master mode, SS/P1.4 is ignored and

may be used as a general-purpose input or output. In slave mode, SS must be driven low to

select an individual device as a slave. When SS is driven high, the slave’s SPI port is deacti-

vated and the MOSI/P1.5 pin can be used as a general-purpose input.

Figure 19-1. SPI Master-Slave Interconnection

Figure 19-2. SPI Block Diagram

8-Bit Shift Register

Master

Clock Generator

SPI

MISO

Slave

MISO

MOSI MOSI

SCK

MSB

LSB

MSB

LSB

Oscillator

8-bit Shift Register

Read Data Buffer

SPI Control

SPI Status Register

SPI Interrupt

Request

Internal

Data Bus

Select

SPI Clock (Mater)

Divider

÷4÷8÷32÷64

SPI Control Register

MSTR

Clock

Logic

Clock

MSB

LSB

MISO

P1.6

MOSI

P1.5

SCK

1.7

P1.4

SPE

Write Data Buffer

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