AT90SCR100_09 datasheet(97/433 Pages) ATMEL

97 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

symmetry around BOTTOM the OC0 value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OC0 change that would have happened on the

way up.

13.1.8

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 13-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 13-8.

Timer/Counter Timing Diagram, no Prescaling

Figure 13-9 shows the same timing data, but with the prescaler enabled.

Figure 13-9.

Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

clk

(clk

I/O /1)

TOV0

clk

I/O

TCNT0

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOV0

TCNT0

MAX - 1

MAX

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O /8)

AT90SCR100 Fiches technique(PDF) 97 Page - ATMEL Corporation

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