TLE 4262

Data Sheet

9

Rev. 2.8, 2008-05-19

Figure 5

Time Response

Reset Timing

The power-on reset delay time is defined by the charging time of an external capacitor

C

C

(1)

Definitions:

•

C

•

•

I

•

•

V

AED03010

Thermal

Power-on-Reset

Voltage Dip

Secondary

Overload

at Output

Spike

D,c

Ι

=

V

d

dt

V

Q

Q, rt

V

<

rr

t

at Input

Undervoltage

Shutdown

t

D

V

t

t

t