CPC1466 datasheet(14/15 Pages) CLARE

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CPC1466

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3.2 Printed Circuit Board Layout Pattern

3.2.1 SOIC

3.2.2 MLP

NOTE: As the metallic pad on the bottom of the MLP

package is connected to the substrate of the die, Clare

recommends that no printed circuit board traces or

vias be placed under this area.

3.3 Tape and Reel Packaging

3.3.1 SOIC

1.90

(0.075)

1.27

(0.050)

(inches)

DIMENSIONS

9.30

(0.366)

0.60

(0.024)

DIMENSIONS

(inches)

5.70

(0.224)

0.40

(0.016)

1.15

(0.045)

0.80

(0.031)

1.15

(0.045)

0.65

(0.026)

0.40

(0.016)

0.43

(0.017)

NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2

Tape and Reel Packaging for 16-Pin SOIC Package

Dimensions

(inches)

Embossment

Embossed

Carrier

330.2 Dia

(13.00 Dia)

Top Cover

Tape Thickness

0.102 Max

(0.004 Max)

User Direction of Feed

Top Cover

Tape

P=12.00

(0.47)

0=10.90 + 0.15

(0.429 + 0.010)

0=10.70 + 0.15

(0.421 + 0.01)

W=16.00 + 0.30

(0.630 + 0.010)

0=3.20 + 0.15

(0.193 + 0.01)

1=2.70 + 0.15

(0.106 + 0.01)

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