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LT1007CDWF Fiches technique(PDF) 1 Page - Linear Technology |
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LT1007CDWF Fiches technique(HTML) 1 Page - Linear Technology |
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1 / 2 page ![]() DICE/DWF SPECIFICATION 1 LT1007 1007dice/dwffa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. PAD FUNCTION 1. 2. 3. 4. 5. 6. 7. 8. VOS TRIM –IN +IN V– NO CONNECT OUT V+ VOS TRIM Backside (substrate) is an alloyed gold layer. Connect to V– DIE CROSS REFERENCE LTC Finished Part Number Order Part Number LT1007C LT1007CDICE LT1007C LT1007CDWF* Please refer to LTC standard product data sheet for other applicable product information. *DWF = DICE in wafer form. Low Noise, High Speed Precision Op Amp DICE/DWF ELECTRICAL TEST LIMITS VS = ±15V, VCM = 0V, TA = 25°C. 7 6 8 1 2 3 4 99mils × 83mils, 12mils thick SYMBOL PARAMETER CONDITIONS MIN MAX UNITS VOS Input Offset Voltage (Note 1) 60 μV IOS Input Offset Current 50 nA IB Input Bias Current ±55 nA Input Voltage Range ±11.0 V CMRR Common Mode Rejection Ratio VCM = ±11 110 dB PSRR Power Supply Rejection Ratio VS = ±4V to ±18V 106 dB AVOL Large-Signal Voltage Gain RL ≥ 2k, VO = ±12V RL ≥ 1k, VO = ±10V 5 3.5 V/μV V/μV VOUT Maximum Output Voltage Swing RL ≥ 2k RL ≥ 600Ω ±12.5 ±10.5 V V SR Slew Rate RL ≥ 2k 1.7 V/μs IS Supply Current 4.7 mA Note 1: Input offset voltage measurements are performed by automatic equipment, approximately 0.5 seconds after application of power. |
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