| Moteur de recherche de fiches techniques de composants électroniques |
|
24LC08B-E/MS Fiches technique(PDF) 3 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
24LC08B-E/MS Fiches technique(HTML) 3 Page - Microchip Technology |
|
3 / 30 page ![]() © 2009 Microchip Technology Inc. DS21710J-page 3 24AA08/24LC08B TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS VCC = +1.7V to +5.5V Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions 1FCLK Clock frequency — — — — 400 100 kHz 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 2 THIGH Clock high time 600 4000 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 3TLOW Clock low time 1300 4700 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 4TR SDA and SCL rise time (Note 1) — — — — 300 1000 ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 5TF SDA and SCL fall time — — 300 ns (Note 1) 6THD:STA Start condition hold time 600 4000 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 7TSU:STA Start condition setup time 600 4700 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 8THD:DAT Data input hold time 0 — — ns (Note 2) 9TSU:DAT Data input setup time 100 250 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 10 TSU:STO Stop condition setup time 600 4000 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 11 TAA Output valid from clock (Note 2) — — — — 900 3500 ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 12 TBUF Bus free time: Time the bus must be free before a new transmission can start 1300 4700 — — — — ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 13 TOF Output fall time from VIH minimum to VIL maximum —— — 250 250 ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA08) 14 TSP Input filter spike suppression (SDA and SCL pins) — — 50 ns (Notes 1 and 3) 15 TWC Write cycle time (byte or page) —— 5 ms — 16 — Endurance 1M — — cycles 25°C, (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |