Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

Preview PDF HTML

STM32F101T6U6ATR Fiches technique(PDF) 46 Page - STMicroelectronics

No de pièce STM32F101T6U6ATR
Description  Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101T6U6ATR Fiches technique(HTML) 46 Page - STMicroelectronics

Back Button STM32F101T6U6ATR Datasheet HTML 42Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 43Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 44Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 45Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 46Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 47Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 48Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 49Page - STMicroelectronics STM32F101T6U6ATR Datasheet HTML 50Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 46 / 73 page
background image
Electrical characteristics
STM32F101x4, STM32F101x6
46/74
Doc ID 15058 Rev 3
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 8.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 25.
Low-power mode wakeup timings
Symbol
Parameter
Typ
Unit
tWUSLEEP
(1)
1.
The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
Wakeup from Sleep mode
1.8
µs
tWUSTOP
(1)
Wakeup from Stop mode (regulator in run mode)
3.6
µs
Wakeup from Stop mode (regulator in low-power mode)
5.4
tWUSTDBY
(1)
Wakeup from Standby mode
50
µs
Table 26.
PLL characteristics
Symbol
Parameter
Value
Unit
Min(1)
Typ
Max(1)
1.
Based on device characterization, not tested in production.
fPLL_IN
PLL input clock(2)
2.
Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
18.0
25
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
36
MHz
tLOCK
PLL lock time
200
µs
Jitter
Cycle-to-cycle jitter
300
ps



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


Fiches technique Télécharger

Go To PDF Page


Lien URL



ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Lien vers la fiche technique    |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com