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PCS809PIURF Fiches technique(PDF) 2 Page - PulseCore Semiconductor |
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PCS809PIURF Fiches technique(HTML) 2 Page - PulseCore Semiconductor |
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2 / 8 page ![]() January 2007 PCS809/PCS810 rev 0.2 3-Pin µP Voltage Supervisor 2 of 8 Notice: The information in this document is subject to change without notice. 1 2 3 Pin Diagram Pin Description Block Diagrams Pin# PCS809 PCS810 Pin Name Description 1 1 GND Ground. 2 - RESET RESET is asserted LOW if VCC falls below VTH. RESET remains LOW for atleast 140ms (TRST) once VCC exceeds the Threshold. In addition, RESET is active LOW - 2 RESET RESET is asserted HIGH if VCC falls below VTH. RESET remains HIGH for atleast 140ms (TRST) once VCC exceeds the threshold. In addition, RESET is active HIGH 3 3 VCC Power supply input voltage (3.0V, 3.3V, 5.0V) GND VCC RESET (RESET) PCS809 (PCS810) Reset Generator Bandgap R1 R2 VCC GND Push-Pull Type RESET (RESET) N-ch Open-Drain Type Reset Generator Bandgap R1 R2 VCC GND RESET NMOS |
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