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SN74LVC112ADE4 Fiches technique(PDF) 2 Page - Texas Instruments

No de pièce SN74LVC112ADE4
Description  DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
PDF  13 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

SN74LVC112ADE4 Fiches technique(HTML) 2 Page - Texas Instruments

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PRE
CLK
K
Q
Q
CLR
J
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289L – JANUARY 1993 – REVISED AUGUST 2005
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H(1)
H(1)
H
H
↓
L
L
Q0
Q 0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
Toggle
H
H
H
X
X
Q0
Q 0
(1)
The output levels in this configuration may not meet the minimum
levels for VOH. Furthermore, this configuration is nonstable; that is,
it does not persist when either PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)
2



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