SN54F86, SN74F86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SDFS019B – JANUARY 1989 – REVISED JANUARY 1997

1

POST OFFICE BOX 655303

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These devices contain four independent 2-input

exclusive-OR gates. They perform the Boolean

function Y = A

⊕ B or Y = AB + AB in positive logic.

A common application is as a true/complement

element. If one of the inputs is low, the other input

is reproduced in true form at the output. If one of

the inputs is high, the signal on the other input is

reproduced inverted at the output.

The SN54F86 is characterized for operation over

the full military temperature range of –55

°C to

125

°C. The SN74F86 is characterized for

operation from 0

°C to 70°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

L

L

L

L

HH

H

LH

H

H

L

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

1Y

3

2Y

6

3Y

8

4Y

11

= 1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

Copyright

© 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

SN54F86 ...J PACKAGE

SN74F86 ...D OR N PACKAGE

(TOP VIEW)

SN54F86 . . . FK PACKAGE

(TOP VIEW)

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y