SN54LS173AW datasheet(6/19 Pages) TI

6 / 19 page

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TA = 25°C, RL = 400 Ω (see Figure 1)

PARAMETER

TEST CONDITIONS

SN54173

SN74173

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

fmax

Maximum clock frequency

MHz

tPHL

Propagation delay time,

high-to-low-level output from clear input

tPLH

Propagation delay time,

low-to-high-level output from clock input

CL = 50 pF

tPHL

Propagation delay time,

high-to-low-level output from clock input

tPZH

Output enable time to high level

tPZL

Output enable time to low level

tPHZ

Output disable time from high level

CL =5 pF

tPLZ

Output disable time from low level

CL = 5 pF

SN54LS173AW Fiches technique(PDF) 6 Page - Texas Instruments

SN54LS173AW Fiches technique(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Fiches technique Télécharger

Lien URL