EP2S15 datasheet(13/238 Pages) ALTERA

13 / 238 page

Altera Corporation

2–5

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

Figure 2–3. Direct Link Connection

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its ALMs.

The control signals include three clocks, three clock enables, two

asynchronous clears, synchronous clear, asynchronous preset/load, and

synchronous load control signals. This gives a maximum of 11 control

signals at a time. Although synchronous load and clear signals are

generally used when implementing counters, they can also be used with

other functions.

Each LAB can use three clocks and three clock enable signals. However,

there can only be up to two unique clocks per LAB, as shown in the LAB

control signal generation circuit in Figure 2–4. Each LAB's clock and clock

enable signals are linked. For example, any ALM in a particular LAB

using the labclk1 signal also uses labclkena1. If the LAB uses both

the rising and falling edges of a clock, it also uses two LAB-wide clock

signals. De-asserting the clock enable signal turns off the corresponding

LAB-wide clock.

Each LAB can use two asynchronous clear signals and an asynchronous

load/preset signal. By default, the Quartus II software uses a NOT gate

push-back technique to achieve preset. If you disable the NOT gate

push-up option or assign a given register to power up high using the

Quartus II software, the preset is achieved using the asynchronous load

ALMs

Direct link

interconnect

to right

Direct link interconnect from

right LAB, TriMatrix memory

block, DSP block, or IOE output

Direct link interconnect from

left LAB, TriMatrix memory

block, DSP block, or IOE output

Local

Interconnect

Direct link

interconnect

to left

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