LTC1041CS8 datasheet(4/8 Pages) LINER

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LTC1041

1041fa

APPLICATIO S I FOR ATIO

The LTC1041 uses sampled data techniques to achieve

its unique characteristics. It consists of two comparators,

each of which has two differential inputs (Figure 1a).

When the sum of the voltages on a comparator’s inputs is

positive, the output is high and when the sum is negative,

the output is low. The inputs are interconnected such that

the RS flip-flop is reset (ON/OFF = GND) when

VIN > (SET POINT + DELTA) and is set (ON/OFF = V+) when

VIN < (SET POINT – DELTA). This makes a very precise

hysteresis loop of 2 • DELTA centered around the

SET POINT. (See Figure 1b.)

For RS < 10kΩ

The dual differential input structure is made with CMOS

switches and a precision capacitor array. Input

impedance characteristics of the LTC1041 can be

determined from the equivalent circuit shown in Figure 2.

The input capacitance will charge with a time constant of

VP-P Output Voltage

vs Load Current

RIN vs Sampling Frequency

LOAD CURRENT, IL (mA)

0.8

0.4

LTC1041 • TPC06

1.2

1.6

2.0

0.6

0.2

1.0

1.4

1.8

V+ = 2.8V

V+ = 16V

V+ = 5V

V+ = 10V

SAMPLING FREQUENCY fS (Hz)

107

109

1011

102

104

103

LTC1041 • TPC07

108

1010

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1041 • AI01a

OSC

(6)

GND

(4)

DELTA

(5)

SET POINT

(3)

VIN

(2)

CEXT

REXT

POWER ON

VP-P

(7)

V+

(8)

ON/OFF

(1)

V+

µs

–

COMP B

TIMING

GENERATOR

VP-P

CIRCUIT

–

COMP A

(a)

LTC1041 • AI01b

V+

GND

INPUT VOLTAGE, VIN

SET POINT

DEADBAND

DELTA – +DELTA

Figure 1. LTC1041 Block Diagram

(b)

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