AT89C51AC3-RDTIM datasheet(100/140 Pages) ATMEL

100 / 140 page

100

AT89C51AC3

4383D–8051–02/08

PCA Registers

Table 50. CMOD Register

CMOD (S:D9h)

PCA Counter Mode Register

Reset Value = 00XX X000b

CIDL

WDTE

CPS1

CPS0

ECF

Bit

Number

Bit

Mnemonic Description

CIDL

PCA Counter Idle Control bit

Clear to let the PCA run during Idle mode.

Set to stop the PCA when Idle mode is invoked.

WDTE

WatchDog Timer Enable

Clear to disable WatchDog Timer function on PCA Module 4,

Set to enable it.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2-1

CPS1:0

EWC Count Pulse Select bits

CPS1 CPS0

Clock source

Internal Clock, FPca/6

Internal Clock, FPca/2

Timer 0 overflow

External clock at ECI/P1.2 pin (Max. Rate = FPca/4)

ECF

Enable PCA Counter Overflow Interrupt bit

Clear to disable CF bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

AT89C51AC3-RDTIM Fiches technique(PDF) 100 Page - ATMEL Corporation

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