CS42435-DMZ datasheet(39/57 Pages) CIRRUS

39 / 57 page

DS685F2

CS42435

7. REGISTER DESCRIPTION

All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read

only. See the following bit-definition tables for bit assignment information. The default state of each bit after a power-

up sequence or reset is listed in each bit description.

7.1

Memory Address Pointer (MAP)

Not a register

7.1.1

Increment (INCR)

Default = 1

Function:

Memory address pointer auto increment control

0 - MAP is not incremented automatically.

1 - Internal MAP is automatically incremented after each read or write.

7.1.2

Memory Address Pointer (MAP[6:0])

Default = 0000001

Function:

Memory address pointer (MAP). Sets the register address that will be read or written by the control port.

7.2

Chip I.D. and Revision Register (Address 01h) (Read Only)

7.2.1

Chip I.D. (CHIP_ID[3:0])

Default = 0001

Function:

I.D. code for the CS42435. Permanently set to 0000.

7.2.2

Chip Revision (REV_ID[3:0])

Default = xxxx

Function:

CS42435 revision level. Revision A is coded as 0001.

432

INCR

MAP6

MAP5

MAP4

MAP3

MAP2

MAP1

MAP0

432

Chip_ID3

Chip_ID2

Chip_ID1

Chip_ID0

Rev_ID3

Rev_ID2

Rev_ID1

Rev_ID0

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