PCA2002 datasheet(13/25 Pages) NXP

13 / 25 page

PCA2002_5

Product data sheet

Rev. 05 — 11 November 2008

13 of 25

NXP Semiconductors

PCA2002

32 kHz watch circuit programmable output period and pulse width

Characteristics

[1]

RL and CL are a load resistor and load capacitor, externally connected to pad RESET.

Table 9.

Characteristics

VDD = 1.55 V; VSS =0V; fosc = 32.768 kHz; Tamb =25 °C; quartz crystal: Rs =40kΩ, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

VDD

supply voltage

normal operating mode;

Tamb = −10 °C to +60 °C

1.1

1.55

3.6

∆VDD

supply voltage variation

∆V/∆t=1V/µs

0.25

IDD

supply current

between motor pulses

120

between motor pulses at

VDD = 3.5 V

120

180

Tamb = −10 °C to +60 °C

200

stop mode;

pin RESET connected to VDD

100

135

Motor output

Vsat

saturation voltage

Rmotor =2kΩ;

Tamb = −10 °C to +60 °C

150

200

Zo(sc)

output impedance (short

circuit)

between motor pulses;

Imotor <1mA

200

300

Ω

Oscillator

Vstart

start voltage

1.1

transconductance

Vi(osc) ≤ 50 mV(p-p)

µS

tstartup

start-up time

0.3

0.9

∆f/f

frequency stability

∆VDD = 100 mV

0.05

0.2

ppm

CL(itg)

integrated load

capacitance

4.3

5.2

6.3

Rpar

parasitic resistance

allowed resistance between

adjacent pins

Ω

Pad RESET

output frequency

VO(dif)

differential output voltage

RL =1MΩ; CL =10pF

[1] 1.4

rise time

RL =1MΩ; CL =10pF

[1] -1

µs

fall time

RL =1MΩ; CL =10pF

[1] -1

µs

Ii(AV)

average input current

pin RESET connected to VDD

or VSS

-10

PCA2002 Fiches technique(PDF) 13 Page - NXP Semiconductors

PCA2002 Fiches technique(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Fiches technique Télécharger

Lien URL